View MU9C1965L-50TCC_7691230.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data sheet mu9c1965a/l lancam a mp lancam, the music logo, and the phrase music semiconductors are registered trademarks of music semiconductors. music is a trademark of music semiconductors. certain features of this device are patented under us patent 5,383,146. 1 october 1998 rev. 1a block diagram /w /e /cm /ec dq31-0 (32) i/ o b u ff e r s data (128) co ntro l logic cam array 1k w ords x 128 bits comparand mask register 1 mask register 2 ad dr e ss d e co d er 1k x 2 val idi ty bit s pr io ri t y en c od er fl ag logic /ff /fi /m f /m i com mands & status 2 10 co ntro l and st atus regis t ers 12 (32) mux demux source and destina tion segment counters data (128) (32) / reset /m m /m a (32) application benefits the 128 bit x 1024 lancam mp facilitates numerous operations: ? simplified switching/routing address filtering and translation ? improved vlan mapping: ? da, sa, port id to vlan id ? filter on any field ? ip to mac, mac to ip filters and translation ? da, sa to atm vc ? shiftable comparand and mask register 2 assists proximate matching algorithms distinctive characteristics ? 1024 x 128-bit cmos content-addressable memory (cam) ? 32-bit i/o ? fast 50 ns compare speed ? dual configuration register set for rapid context switching ? 32-bit cam/ram segments with musics patented partitioning ? /ma and /mm output flags enable faster system performance ? readable device id ? selectable faster operating mode with no wait states after a no-match ? validity bit setting accessible from the status register ? single cycle reset for segment control register ? 80-pin tqfp package ? 5 volt (1965a) or 3.3 volt (1965l) operation
mu9c1965a/l lancam a a a a a mp rev. 1a 2 general description the mu9c1965a and mu9c1965l lancam a mps are 1024 x 128-bit content-addressable memories (cams), featuring a 32-bit wide interface. the wide comparand width allows the lancam mp to handle multiple protocols in a single search table device. content-addressable memories, also known as associative memories, operate in the converse way to random access memories (ram). in a ram, the input to the device is an address and the output is the data stored at that address. in a cam, the input is a data sample and the output is a flag to indicate a match and the address of the matching data. as a result, a cam searches large databases for matching data in a short, constant time period, no matter how many entries are in the database. the ability to search data words up to 128 bits wide allows large address spaces to be searched rapidly and efficiently. a patented architecture links each cam entry to associated data and makes this data available for use after a successful compare operation. the music lancam mp is ideal for address filtering and translation applications in lan and atm switches and routers that need the wide comparand for virtual lans, vc translation, or ipv6 address recognition. the 128-bit cam width is enough to include the da, sa, port id, and virtual lan id for lan switches, or da, sa, and vc for atm switches. the lancam mp is also well suited for encryption, database accelerators, and image processing. to use the lancam mp, the user loads the data into the comparand register, which is automatically compared to all valid cam locations. the device then indicates whether or not one or more of the valid cam locations contains data that matches the target data. the status of each cam location is determined by two validity bits at each memory location. the two bits are encoded to render four validity conditions: valid, skip, empty, and random access, as shown in table 1. the memory can be partitioned into cam and associated ram segments on 32-bit boundaries, but by using one of the two available mask registers, the cam/ ram partitioning can be set at any arbitrary size between zero and 128 bits. the lancam mps internal data path is 128 bits wide for rapid internal comparison and data movement. vertical cascading of additional lancam mps in a daisy chain fashion extends the cam memory depth for large databases. cascading requires no external logic. loading data to the control, comparand, and mask registers automatically triggers a compare. compares may also be initiated by a command to the device. associated ram data is available immediately after a successful compare operation. the status register reports the results of compares including all flags and addresses. two mask registers are available and can be used in two different ways: to mask comparisons or to mask data writes. the random access validity type allows additional masks to be stored in the cam array where they may be retrieved rapidly. a simple four-wire control interface and commands loaded into the instruction decoder control the device. a powerful instruction set increases the control flexibility and minimizes software overhead. additionally, dedicated pins for match and multiple match flags enhance performance when the device is controlled by a state machine. these and other features make the lancam mp a powerful associative memory that drastically reduces search delays. skip bit 0 0 1 1 empty bit 0 1 0 1 entry type valid empty skip ram table 1: entry types vs. validity bits operational overview
mu9c1965a/l lancam a a a a a mp rev. 1a 3 pin descriptions /e (chip enable, input, ttl) the /e input enables the device while low. the falling edge registers the control signals /w, /cm, /ec. the rising edge locks the daisy chain, turns off the dq pins, and clocks the destination and source segment counters. the four cycle types enabled by /e are shown in table 2. /w (write enable, input, ttl) the /w input selects the direction of data flow during a device cycle. /w low selects a write cycle and /w high selects a read cycle. /cm (data/command select, input, ttl) the /cm input selects whether the input signals on dq31C0 are data or commands. /cm low selects command cycles and /cm high selects data cycles. /ec (enable daisy chain, input, ttl) the /ec signal performs two functions. the /ec input enables the /mf output to show the results of a comparison, as shown in figure 5 on page 15. if /ec is low at the falling edge of /e in a given cycle, the /mf output is enabled. otherwise, the /mf output is held high. the /ec signal also enables the /mfC/mi daisy chain, which serves to select the device with the highest-priority match in a string of lancams. tables 6a and 6b on page 12 explain the effect of the /ec signal on a device with or without a match in both standard and enhanced modes. /ec must be high during initialization. dq31C0 (data bus, i/o, ttl) the dq31C0 lines convey data, commands, and status to and from the lancam mp, as shown in table 3. /w and /cm control the direction and nature of the information that flows to or from the device. when /e is high, dq31C0 go to hi-z. /mf (match flag, output, ttl) the /mf output goes low when one or more valid matches occur during a compare cycle. /mf becomes valid after /e goes high on the cycle that enables the daisy chain (on the first cycle that /ec is registered low by the previous falling edge of /e; see figure 5 on page 15). in a daisy chain, valid match(es) in higher priority devices are passed from the /mi input to /mf. if the daisy chain is enabled but the match flag is disabled in the control register, the /mf output only depends on the /mi input of the device (/mf= /mi). /mf is high if there is no match or when the daisy chain is disabled (/e goes high when /ec was high on the previous falling edge of /e). the system match flag is the /mf pin of the last device in the daisy chain. /mf will be reset when the active configuration register set is changed. table 2: i/o cycles /w low low high high /cm low high low high cycle type command write cycle data write cycle command read cycle data read cycle all signals are implemented in cmos technology with ttl levels. signal names that start with a slash (/) are active low. inpu ts should never be left floating. the cam architecture draws large currents during compare operations, mandating the use of good l ayout and bypassing techniques. refer to the electrical characteristics section for more information. pinout diagram 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 gnd gnd dq9 dq10 dq11 nc vcc vcc test2 nc gnd gnd dq12 dq13 gnd gnd dq14 dq15 dq16 nc 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 gn d gn d dq17 dq18 dq19 gn d dq20 vc c dq21 dq22 dq23 dq24 dq25 gn d gn d dq26 dq27 dq28 dq29 gn d gn d dq8 dq7 dq6 dq5 gn d gn d dq4 dq3 dq2 dq1 dq0 vc c vc c /ec /cm /ma /f i gn d gn d nc /ff /mi /mf /mm gnd gnd /reset vcc vcc /e /w vcc vcc test1 nc dq31 dq30 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80-pin tqfp (top view)
mu9c1965a/l lancam a a a a a mp rev. 1a 4 pin descriptions continued /mi (match input, input, ttl) the /mi input prioritizes devices in vertically cascaded systems. it is connected to the /mf output of the previous device in the daisy chain. the /mi pin on the first device in the chain must be tied high. /ma (device match flag, output, ttl) the /ma output is low when one or more valid matches occur during the current or the last previous compare cycle. the /ma output is not qualified by /ec or /mi, and reflects the match flag from that specific devices status register. /ma will be reset when the active register set is changed. /mm (device multiple match flag, output, ttl) the /mm output is low when more than one valid match occurs during the current or the last previous compare cycle. the /mm output is not qualified by /ec or /mi, and reflects the multiple match flag from that specific devices status register. /mm will be reset when the active register set is changed. /ff (full flag, output, ttl) if enabled in the control register, the /ff output goes low when no empty memory locations exist within the device (and in the daisy chain above the device as indicated by the /fi pin). the system full flag is the /ff pin of the last device in the daisy chain, and the next free address resides in the device with /fi low and /ff high. if disabled in the control register, the /ff output only depends on the /fi input (/ff = /fi). /fi (full input, input, ttl) the /fi input generates a cam-memory-system-full indication in vertically cascaded systems. it is connected to the /ff output of the previous device in the daisy chain. the /fi pin on the first device in a chain must be tied low. /reset (reset, input, ttl) /reset must be driven low to place the device in a known state before operation, which will reset the device to the conditions shown in table 5 on page 10. the /reset pin should be driven by ttl levels, not directly by an rc timeout. /e must be kept high during /reset. test1, test2 (test, input, ttl) these pins enable music production test modes that are not usable in an application. they should be connected to ground, either directly or through a pull-down resistor, or they may be left unconnected. these pins may not be implemented on all versions of this product. vcc, gnd (positive power supply, ground) these pins are the power supply connections to the lancam mp. vcc must meet the voltage supply requirements in the operating conditions section relative to the gnd pins, which are at 0 volts (system reference potential), for correct operation of the device. all the ground and power pins must be connected to their respective planes with adequate bulk and high frequency bypassing capacitors in close proximity to the device. note: -90 or slower switching characteristics can be operated without the gnd connections on pins 1, 2, 20, 21, 22, 41, 42, 60, 61, and 62. music, however, recommends the usage of these gnd connections to ensure full compatibility with future products. table 3: dq bus multiplexing /w low high low high /cm low low high high cycle type command write command read tco 2nd cycle data write data read f bit 0 1 0 1 x x x x dq31C16 non-tco instruction non-tco instruction tco instruction (read register)* tco instruction (write register) status register bits 31C16 status register bits 31C16? data to cr, mrx, mem. data from cr, mrx, mem. dq15C0 xxxx absolute address xxxx value to register status register bits 15C0 register contents* data to cr, mrx, mem. data from cr, mrx, mem. notes: * ? a cw of a tco instruction with the f bit set to 0 sets up a register read in the following cycle. the following cycle must be a command read cycle, otherwise the register read will be cancelled. upper 16 bits will be status register bits 31C16, except for a read of the page address register, in which case they will be all zeros.
mu9c1965a/l lancam a a a a a mp rev. 1a 5 the lancam mp is a content-addressable memory (cam) with a 32-bit i/o for network address filtering and translation, virtual memory, data compression, caching, and table lookup applications. the memory consists of static cam, organized in 128-bit data fields. each data field can be partitioned into a cam and a ram subfield on 32-bit boundaries. the contents of the memory can be randomly accessed or associatively accessed by the use of a compare. during automatic comparison cycles, data in the comparand register is automatically compared with the valid entries in the memory array. the device id can be read using a tco ps instruction (see table 13 on page 23). the data inputs and outputs of the lancam mp are multiplexed for data and instructions over a 32-bit i/o bus. internally, data is handled on a 128-bit basis, since the comparand register, the mask registers, and each memory entry are 128 bits wide. memory entries are globally configurable into cam and ram segments on 32-bit boundaries, as described in us patent 5,383,146 assigned to music semiconductors. seven different cam/ram splits are possible, with the cam width going from one to four segments, and the remaining ram width going from three to zero segments. finer resolution on compare width is possible by invoking a mask register during a compare, which does global masking on a bit basis. the cam subfield contains the associative data, which enters into compares, while the ram subfield contains the associated data, which is not compared. in lan bridges, the ram subfield can hold, for example, port-address and aging information related to the destination or source address information held in the cam subfield of a given location. in a translation application, the cam field can hold the dictionary entries, while the ram field holds the translations, with almost instantaneous response. each entry has two validity bits (known as skip bit and empty bit) associated with it to define its particular type: empty, valid, skip, or ram. when data is written to the active comparand register, and the active segment control register reaches its terminal count, the contents of the comparand register are automatically compared with the cam portion of all the valid entries in the memory array. for added versatility, the comparand register can be barrel-shifted right or left one bit at a time. a compare instruction can then be used to force another compare between the comparand register and the cam portion of memory entries of any one of the four validity types. after a read or move from memory operation, the validity bits of the location read or moved will be copied into the status register, where they can be read from the status register using command read cycles. data can be moved from one of the data registers (cr, mr1, or mr2) to a memory location that is based on the results of the last comparison (highest-priority match or next free), or to an absolute address, or to the location pointed to by the active address register. data can also be written directly to the memory from the dq bus using any of the above addressing modes. the address register may be directly loaded and may be set to increment or decrement, allowing dma-type reading or writing from memory. two sets of configuration registers (control, segment control, address, mask register 1, and persistent source and destination) are provided to permit rapid context switching between foreground and background activities. the currently active set of configuration registers control writes, reads, moves, and compares. the foreground set would typically be pre-loaded with values useful for comparing input data, often called filtering, while the background set would be pre-loaded with values useful for housekeeping activities such as purging old entries. moving from the foreground task of filtering to the background task of purging can be done by issuing a single instruction to change the current set of configuration registers. the match condition of the device is reset whenever the active register set is changed. the active control register determines the operating conditions within the device. conditions set by this registers contents are reset, enable or disable match flag, enable or disable full flag, cam/ram partitioning, disable or select masking conditions, disable or select auto-incriminating or decrimenating the address register, and select standard or enhanced mode. the active segment control register contains separate counters to control the writing of 32-bit data segments to the selected persistent destination, and to control the reading of 32-bit data segments from the selected persistent source. there are two active mask registers at any one time, which can be selected to mask comparisons or data writes. mask register 1 has both a foreground and background mode to support rapid context switching. functional description
mu9c1965a/l lancam a a a a a mp rev. 1a 6 functional description continued mask register 2 does not have this mode, but can be shifted left or right one bit at a time. for masking comparisons, data stored in the active selected mask register determines which bits of the comparand are compared against the valid contents of the memory. if a bit is set high in the mask register, the same bit position in the comparand register becomes a dont care for the purpose of the comparison with all the memory locations. during a data write cycle or a mov instruction, data in the specified active mask register can also determine which bits in the destination will be updated. if a bit is high in the mask register, the corresponding bit of the destination is unchanged. the match line associated with each memory address is fed into a priority encoder where multiple responses are resolved, and the address of the highest-priority responder (the lowest numerical match address) is generated. in lan applications, a multiple response might indicate an error. in other applications the existence of multiple responders may be valid. four input control signals and commands loaded into an instruction decoder control the lancam mp. two of the four input control signals determine the cycle type. the control signals tell the device whether the data on the i/o bus represents data or a command, and is input or output. commands are decoded by instruction logic and control moves, forced compares, validity bit manipulations, and the data path within the device. registers (control, segment control, address, next free address, etc.) are accessed using temporary command override instructions. the data path from the dq bus to/from data resources (comparand, masks, and memory) within the device are set until changed by select persistent source and destination instructions. after a compare cycle (caused by either a data write to the comparand or mask registers, a write to the control register, or a forced compare), the status register contains the address of the highest-priority matching location in that device, concatenated with its page address, along with flags indicating internal match, multiple match, and full. when the status register is read with a command read cycle, the device with the highest-priority match will respond, outputting the system match address to the dq bus. the internal match (/ma) and multiple match (/mm) flags are also output on pins. another set of flags (/mf and /ff) that are qualified by the match and full flags of previous devices in the system are also available directly on output pins, and are independently daisy-chained to provide system match and full flags in vertically cascaded lancam arrays. in such arrays, if no match occurs during a comparison, read access to the memory and all the registers except the next free register is denied to prevent device contention. in a daisy chain, all devices will respond to command and data write cycles, depending on the conditions shown in tables 6a and 6b on page 12, unless the operation involves the highest-priority match address or the next free address; in which case, only the specific device having the highest-priority match or the next free address will respond. a page address register in each device simplifies vertical expansion in systems using more than one lancam. this register is loaded with a specific device address during system initialization, which then serves as the higher-order address bits. a device select register allows the user to target a specific device within a vertically cascaded system by setting it equal to the page address register value, or to address all the devices in a string at the same time by setting the device select value to ffffh. figure 1a shows expansion using a daisy chain. note that system flags are generated without the need for external logic. the page address register allows each device in the vertically cascaded chain to supply its own address in the event of a match, eliminating the need for an external priority encoder to calculate the complete match address at the expense of the ripple through time to resolve the highest- priority match. the full flag daisy chaining allows associative writes using a move to next free address instruction which does not need a supplied address. figure 1b shows an external pld implementation of a simple priority encoder that eliminates the daisy chain ripple through delays for systems requiring maximum performance from many cams.
mu9c1965a/l lancam a a a a a mp rev. 1a 7 functional description continued figure 1a: vertical cascading vcc system full syste m match /mi /fi /ff /mf lancam mp 32 /e /w /cm /ec dq31-0 /mi /fi /ff /mf /mi /fi /ff /mf /e /w /cm /ec dq31-0 /e /w /cm /ec dq31-0 /e /w /cm /ec dq31-0 lancam mp lancam mp figure 1b: external prioritizing /ma /ma /ma /ma lancam m p /mi /mi /mi /mi vcc system match pld lancam m p lancam m p lancam m p
mu9c1965a/l lancam a a a a a mp rev. 1a 8 operational characteristics throughout the following, aaah represents a three-digit hexadecimal number aaa, while bbb represents a two-digit binary number bb. all memory locations are written to or read from in 32-bit segments. segment 0 corresponds to the lowest order bits (bits 31C0) and segment 3 corresponds to the highest order bits (bits 127C96). the control bus refer to the block diagram on page 1 for the following discussion. the inputs chip enable (/e), write enable (/w), command enable (/cm), and enable daisy chain (/ec) are the primary control mechanism for the lancam mp. the /ec input of the control bus enables the /mf match flag output when low and controls the daisy chain operation. instructions are the secondary control mechanism. logical combinations of the control bus inputs, coupled with the execution of select persistent source (sps), select persistent destination (spd), and temporary command override (tco) instructions allow the i/o operations to and from the dq31C0 lines to the internal resources, as shown in table 4. the comparand register is the default source and destination for data read and write cycles. this default state can be overridden independently by executing a select persistent source or select persistent destination instruction, selecting a different source or destination for data. subsequent data read or data write cycles will access that source or destination until another sps or spd instruction is executed. the currently selected persistent source or destination can be read back through a tco ps or pd instruction. the sources and destinations available for persistent access are those resources on the 128-bit bus: comparand register, mask register 1, mask register 2, and the memory array. the default destination for command write cycles is the instruction decoder, while the default source for command read cycles is the status register. the entire 32-bit status register is read in a single cycle. temporary command override (tco) instructions provide access to the control register, the page address register, the segment control register, the address register, the next free address register, and device select register. these instructions are only active for one command write cycle to write a value into a register, or one command write cycle followed by a command read cycle to read a registers contents. each of these 16-bit registers is read out on the dq15C0 pins, with the upper 16 bits of the status register output on the dq31C16 pins (except in the case of a page address register read where 0s will be read on dq31C16 instead), as shown in table 3 on page 4. the data and control interfaces to the lancam mp are synchronous. during a write cycle, the control and data inputs are registered by the falling edge of /e. when writing to the persistently selected data destination, the destination segment counter is clocked by the rising edge of /e. during a read cycle, the control inputs are registered by the falling edge of /e, and the data outputs are enabled while /e is low. when reading from the persistently selected data source, the source segment counter is clocked by the rising edge of /e. the register set the control, segment control, address, mask register 1, and the persistent source and destination registers are duplicated, with one set termed the foreground set, and the other the background set. the active set is chosen by issuing select foreground registers or select background registers instructions. by default, the foreground set is active after a reset. having two alternate sets of registers that determine the device configuration allows for a rapid return to a foreground network filtering task from a background housekeeping task. writing a value to the control register or writing data to the last segment of the comparand or either mask register will cause an automatic comparison to occur between the contents of the comparand register and the words in the cam segments of the memory marked valid, masked by mr1 or mr2 if selected in the control register. instruction decoder the instruction decoder is the write-only decode logic for instructions and is the default destination for command write cycles using the dq31C16 lines. if the instruction requires an absolute address or register value, the f address field flag (bit 11) of the instruction is set to a 1, and the data on the dq15C0 lines are written to the proper register in that same cycle. if the instruction written is a tco, and the f bit is not set, the contents of the register specified by the tco may be read back by a successive command read cycle to the dq15C0 signal lines.
mu9c1965a/l lancam a a a a a mp rev. 1a 9 table 4: input/output operations /cm l l h h x /w l h l h x i/o status in in in in in in in out out out out out out out out high-z in in in in in in in out out out out out high-z high-z operation load instruction decoder load address register load control register load page address register load segment control register load device select register deselected read next free address register read address register read status register bits 31C0 read control register read page address register read segment control register read device select register read current persistent source or destination deselected load comparand register load mask register 1 load mask register 2 write memory array at address write memory array at next free address write memory array at highest-priority match deselected read comparand register read mask register 1 read mask register 2 read memory array at address read memory array at highest-priority match deselected deselected cycle type cmd write cmd read data write data read /e l l l l h notes 1 2 2 2 2 2 9 3 3 4 3 3 3 3 3, 10 9 5, 8 6, 8 6, 8 6, 8 6, 8 6, 8 9 5, 8 7, 8 7, 8 7, 8 7, 8 9 sps spd tco notes: 1. default command write cycle destination (does not require a tco instruction). 2. to load a value into a register using a tco instruction takes one command write cycle with the f bit equal to 1, and the value to be loaded into the selected register placed in dq15C0. 3. reading the contents of a register using a tco instruction takes two cycles. the first cycle is a command write of a tco instruction with the f bit equal to 0. if the next cycle is a command read, the value stored in the selected register will be read out on the dq15C0 lines. additionally, bits 31C16 of the status register will be read out on the dq31C16 lines, except in the case of a page address read where 0s will be read on dq31C16 instead. 4. default command read cycle source (does not require a tco instruction). 5. default persistent source and destination after reset. if other resources were sources or destinations, spd cr or sps cr restores the comparand register as the destination or source. 6. selected by executing a select persistent destination instruction. 7. selected by executing a select persistent source instruction. 8. access is performed in one or two 32-bit read or write cycles. the segment control register is used to control the selection of the desired 32-bit segement(s) by establishing the segment counters limits and start values. 9. device is deselected if device select register setting does not equal page address register setting, unless the device select register is set to ffffh which allows only write access to the device, except in the case of a match. (writes to the device select register are always active.) device may also be deselected under locked daisy chain conditions as shown in tables 6a and 6b on page 12. 10. a command read cycle after a tco ps or tco pd reads back the instruction decoder bits that were last set to select a persistant source or destination. the tco ps instruction will also read back the device id. operational characteristics continued
mu9c1965a/l lancam a a a a a mp rev. 1a 10 if the address field flag is set in a memory access instruction, the absolute address supplied on the dq15C0 lines will automatically load the address register and the instruction will execute at this new address. if the address field flag is not set, the memory access occurs at the address currently contained in the address register. after the execution of the instruction, the address register auto- increments or auto-decrements depending on the setting of control register bits ct3 and ct2. control register (ct) the control register is composed of a number of switches that configure the lancam mp, as shown in table 9 on page 22. it is written or read through dq15C0 using a tco ct instruction on dq31C16. on read cycles, dq31C16 will be the upper 16 bits of the status register. if bit 15 of the value written during a tco ct is a 0, the device is reset (and all other bits are ignored). see table 5 for the reset states. bit 15 always reads back as a 0. a write to the control register causes an automatic compare to occur (except in the case of a reset). either the foreground or background control register will be active, depending on which has been selected, and only the active control register will be written to or read from. if the match flag is disabled through bits 14 and 13, the internal match condition, /ma(int), used to determine a daisy-chained devices response is forced high as shown in tables 6a and 6b on page 12, so that case 6 is not possible, effectively removing the device from the daisy chain. with the match flag disabled, /mf=/mi and operations directed to highest-priority match locations are ignored. normal operation of the device is with the /mf enabled. the match flag enable field has no effect on the /ma or /mm output pins or status register bits. these bits always reflect the true state of the device. if the full flag is disabled through bits 12 and 11, the device behaves as if it is full and ignores instructions to next free address. additionally, writes to the page address register will be disabled. all other instructions operate normally. additionally, with the /ff disabled, /ff=/fi. normal operation of the device is with the /ff enabled. the full flag enable field has no effect on the /fl status register bit. this bit always reflects the true state of the device. control register bits 8C6 control the cam/ram partitioning. the cam portion of each word may be sized from a full 128 bits down to 32 bits in 32-bit increments. the ram portion can be at either end of the 128-bit word. compare masks may be selected by bits 5 and 4. mask register 1, mask register 2, or neither may be selected to mask compare operations. the address register behavior is controlled by bits 3 and 2, and may be set to increment, decrement, or neither after a memory access. bits 1 and 0 set the operating mode: standard as shown in table 6a , or enhanced as shown in table 6b, both shown on page 12. the device will reset to standard mode and follow the operating responses in table 6a. when operating in enhanced mode, it is not necessary to unlock the daisy chain with a nop instruction before command or data writes after a non-matching compare, as required in standard mode. operational characteristics continued table 5: device control state after reset cam status validity bits at all memory locations match and full flag outputs cam/ram partitioning comparison masking address register auto-increment or auto-decrement source and destination segment counters count ranges address register and next free address register page address and device select registers control register after reset (including ct15) persistent destination for command writes persistent source for command reads persistent source and destination for data reads and writes operating mode configuration register set /reset condition skip = 0, empty = 1 (empty) enabled 128 bits cam, 0 bits ram disabled disabled 00b to 11b; loaded with 00b contain all 0s contain all 0s (no change on software reset) contains 0008h instruction decoder status register comparand register standard foreground
mu9c1965a/l lancam a a a a a mp rev. 1a 11 operational characteristics continued segment control register (sc) the segment control register, as shown in table 10 on page 23, is accessed using a tco sc instruction with the register contents placed on dq15C0. on read cycles, dq31C16 will be the upper 16 bits of the status register, and d15, d10, d5, and d2 will always read back as 0s. either the foreground or background segment control register will be active, depending on which set has been selected, and only the active segment control register will be written to or read from. the segment control register contains dual independent incriminating counters with limits; one for data reads and one for data writes. these counters control which 32-bit segment of the 128-bit internal resource is accessed during a particular data cycle on the 32-bit data bus. the actual destination for data writes and source for data reads (called the persistent destination and source) are set independently with spd and sps instructions, respectively. each of the two counters consists of a start limit, an end limit, and the current count value that points to the segment to be accessed on the next data cycle. the current count value can be set to any segment, even if it is outside the range set by the start and end limits. the counters count up from the current count value to the end limit and then jump back to the start limit. if the current count is greater than the end limit, the current count value will increment to 3, then roll over to 0 and continue incriminating until the end limit is reached; it then jumps back to the start limit. if a sequence of data writes or reads is interrupted, the segment control register can be reset to its initial start limit values with the rsc instruction. after the lancam is reset, both source and destination counters are set to count from segment 0 to segment 3 with an initial value of 0. page address register (pa) the page address register is loaded using a tco pa instruction on dq31C16 with a user selected 16-bit value (not ffffh) on dq15C0. during reads of the pa register, dq31C16 will all be 0. the entry in the pa register is used to give a unique address to the different devices in a daisy chain. in a daisy chain, the pa value of each device is loaded using the sff instruction to advance to the next device, as shown in the setting page address register values section on page 17. a software reset (using the control register) does not affect the page address register. device select register (ds) the device select register is used to select a specific (target) device using the tco ds instruction in dq31C16 and setting the 16-bit ds value in dq15C0 equal to the targets pa value. the ds register can be read through dq15C0 with dq31C16 returning the upper 16 bits of the status register. in a daisy chain, setting ds = ffffh will select all devices. however, in this case, the ability to read information out of the device is restricted as shown in tables 6a and 6b. a software reset (using the control register) does not affect the device select register. address register (ar) the address register points to the cam memory location to be operated upon when m@[ar] or m@aaah is part of the instruction. it can be loaded directly by using a tco ar instruction or indirectly by using an instruction requiring an absolute address, such as mov aaah, cr,v. the ar register can be read through dq15C0 with dq31C16 returning the upper 16 bits of the status register. after being loaded, the address register value will then be used for the next memory access referencing the address register. a reset sets the address register to zero. control register bits ct3 and ct2 set the address register to automatically increment or decrement (or not change) during sequences of command or data cycles. the address register will change after executing an instruction that includes m@[ar] or m@aaah, or after a data access to the end limit segment (as set in the segment control register) when the persistent source or destination is m@[ar] or m@aaah. either the foreground or background address register will be active, depending on which set has been selected, and only the active address register will be written to or read from. next free address register (nf) the lancam mp automatically stores the address of the first empty memory location in the next free address register, which is then used as a memory address pointer for m@nf operations. the next free address register, shown in table 11 on page 23, can be read through dq15C0 using a tco nf instruction. dq31C16 will return the upper 16 bits of the status register. by taking /ec low during the tco nf instruction cycle, only the device with /fi low and /ff high will output the contents of its next free address register, which gives the next free address in a system of daisy-chained devices. the next free address may be read from a specific device in the chain by setting the device select register to the value of the desired devices page address and leaving /ec high.
mu9c1965a/l lancam a a a a a mp rev. 1a 12 the full flag daisy chain causes only the device whose /fi input is low and /ff output high to respond to an instruction using the next free address. after a reset, the next free address register is set to zero. status register the 32-bit status register, shown in table 12 on page 23, is the default source for command read cycles. bit 31 is the internal match flag, which will go low if a match was found in this particular device. bit 30 is the internal multiple match flag, which will go low if a multiple match was detected. bit 29 is the internal full flag, which will go low if the particular device has no empty memory locations. bits 28 and 27 are the skip and empty validity bits, which reflect the validity of the last memory location read. after a reset, the skip and empty bits will read 11 until a read or move from memory has occurred. the rest of the status register contains the page address of the device and the address of the highest-priority match. after a reset or a no match condition, the match address bits will be all 1s. operational characteristics continued notes: 1. exceptions are: a) a write to the device select register is always active in all devices; b) a write to the page address register is active in the device with /fi low and /ff high; and c) the set full flag (sff) instruction is active in the device with /fi low and /ff high. 2. if /mf is disabled in the control register, /ma (internal) is forced high preventing a case 6 response. 3. this is no for a mov instruction involving memory at next free address if /fi is high or the device is full. 4. this is no if the persistent destination is memory at next free address and /fi is high or the device is full. 5. for a command read following a tco nf instruction, this is yes if the device contains the first empty location in a daisy cha in (i.e., /fi low and /ff high) and no if it does not. 6. this is no for a mov or vbc instruction involving memory at highest-priority match. 7. this is no if the persistent destination is memory at highest-priority match. table 6a: standard mode device select response case 1 2 3 4 5 6 2 internal /ec(int) 1 1 1 0 0 0 internal /ma (int) x x x x 1 0 external /mi x x x 0 1 1 device select reg. ds=ffffh ds=pa ds 1 ffffh and ds 1 pa x x x command write 1 yes 3 yes 3 no no no yes 3 data write yes 4 yes 4 no no no yes 4 command read no yes no no 5 no 5 yes 5 data read no yes no no no yes table 6b: enhanced mode device select response case 1 2 3 4 5 6 2 internal /ec(int) 1 1 1 0 0 0 internal /ma (int) x x x 0 1 0 external /mi x x x 0 x 1 device select reg. ds = ffffh ds = pa ds 1 ffffh and ds 1 pa x x x command write 1 yes 3 yes 3 no yes 3,6 yes 3,6 yes 3 data write yes 4 yes 4 no yes 4,7 yes 4,7 yes 4 command read no yes no no 5 no 5 yes 5 data read no yes no no no yes
mu9c1965a/l lancam a a a a a mp rev. 1a 13 operational characteristics continued comparand register (cr) the 128-bit comparand register is the default destination for data writes and reads, using the segment control register to select which 32-bit segment of the comparand register is to be loaded or read out. the persistent source and destination for data writes and reads can be changed to the mask registers or memory by sps and spd instructions. during an automatic or forced compare, the comparand register is compared against the cam portion of all memory locations with the correct validity condition simultaneously. automatic compares always compare against valid memory locations, while forced compares, using cmp instructions, can compare against memory locations tagged with any specific validity condition. the comparand register may be shifted one bit at a time to the right or left by issuing a shift right or shift left instruction, with the right and left limits for the wrap around determined by the cam/ram partitioning set in the control register. during shift rights, bits shifted off the lsb of the cam partition will reappear at the msb of the cam partition. likewise, bits shifted off the msb of the cam partition will reappear at the lsb during shift lefts. mask registers (mr1, mr2) the mask registers can be used in two different ways, either to mask compares or to mask data writes and moves. either mask register can be selected in the control register to mask every compare, or selected by instructions to participate in data writes or moves to and from memory. if a bit in the selected mask register is set to a 0, the corresponding bit in the comparand register will enter into a masked compare operation. if a mask bit is a 1, the corresponding bit in the comparand register will not enter into a masked compare operation. bits set to 0 in the mask register cause corresponding bits in the destination register or memory location to be updated when masking data writes or moves, while a bit set to 1 will prevent that bit in the destination from being changed. either the foreground or background mr1 can be set active, but after a reset, the foreground mr1 is active by default. mr2 incorporates a sliding mask, where the data can be replicated one bit at a time to the right or left with no wraparound by issuing a shift right or shift left instruction. the right and left limits are determined by the cam/ram partitioning set in the control register. for a shift right the upper limit bit is replicated to the next lower bit, while for a shift left the lower limit bit is replicated to the next higher bit. the memory array memory organization the memory array is organized into 128-bit words with each word having an additional two validity bits (skip and empty). by default, all words are configured to be 128 cam cells. however, bits 8C6 of the control register can divide each word into a cam field and a ram field. the ram field can be assigned to the least-significant or most- significant portion of each entry. the cam/ram partitioning is allowed on 32-bit boundaries, permitting selection of the configurations shown in table 9 on page 22, bits 8C6 (e.g., 001 sets the 96 msbs to cam and the 32 lsbs to ram). memory array bits designated as ram can be used to store and retrieve data associated with the cam content at the same memory location. memory access there are two general ways to get data into and out of the memory array: directly or by moving the data via the comparand or mask registers. the first way, through direct reads or writes, is set up by issuing a set persistent destination (spd) or set persistent source (sps) command. the addresses for the direct access can be directly supplied, supplied from the address register, supplied from the next free address register, or supplied as the highest-priority match address. additionally, all the direct writes can be masked by either mask register. the second way is to move data via the comparand or mask registers. this is accomplished by issuing data move commands (mov). moves using the comparand register can also be masked by either of the mask registers. i/o cycles the lancam mp supports four basic i/o cycles: data read, data write, command read, and command write, as shown in table 2 on page 3. the type of cycle is determined by the states of the /w and /cm control inputs. these signals are registered at the beginning of a cycle by the falling edge of /e. table 3 on page 4 shows how the /w and /cm lines select the cycle type and how the data bus is utilized for each. during read cycles, the dq31C0 outputs are enabled after /e goes low. during write cycles, the data or command to be written is captured from dq31C0 at the beginning of the cycle by the falling edge of /e. figures 2 and 3 show read and write cycles respectively. figure 4 shows typical
mu9c1965a/l lancam a a a a a mp rev. 1a 14 operational characteristics continued cycle-to-cycle timing with the match flag valid at the end of the comparand write cycle, assuming /ec is low at the start of this cycle. data writes and reads to the comparand, mask registers or memory occur in one to four 32-bit cycles, depending on the settings in the segment control register. the compare operation automatically occurs during data writes to the comparand or mask registers when the destination segment counter reaches the end count set in the segment control register. if there was a match, the second cycle reads status or associated data, depending on the state of /cm. for cascaded devices, /ec needs to be low at the start of the cycle prior to any cycle that requires a locked daisy chain, such as a status register or associated data read after a match. if there is no match in standard mode, the output buffers stay hi-z, and the daisy chain must be unlocked by taking /ec high during a nop or other non-functioning cycle, as indicated in table 6a on page 12. figure 5 shows how the internal /ec timing holds the daisy chain locking effect over into the next cycle. in enhanced mode, this nop is not needed before data or command writes following a non-matching compare, as indicated by table 6b on page 12. a single-chip system does not require daisy-chained match flag operation, hence /ec could be tied high and the /ma pin or flag in the status register used instead of /mf, allowing access to the device regardless of the match condition. figure 4: cycle to cycle timing example /e dq31-0 /w /cm /ec /m f com paran d w rite cyc l e da ta status read cycl e ass oc iat ed d ata read cycle data data /ma and /mm flags updated / m a, /m m match flag valid figure 2: read cycle /e dq31-0 /w /cm /ec dat a ou t figure 3: write cycle /e dq31-0 /w /cm /ec
mu9c1965a/l lancam a a a a a mp rev. 1a 15 operational characteristics continued the minimum timings for the /e control signal are given in the switching characteristics section on page 26. note that at minimum timings the /e signal is non-symmetrical, and that different cycle types have different timing requirements, as given in table 8 on page 22. compare operations during a compare operation, the data in the comparand register is compared to all locations in the memory array simultaneously. any mask register used during compares must be selected beforehand in the control register. there are two ways compares are initiated: automatic and forced compares. automatic compares perform a compare of the contents of the comparand register against memory locations that are tagged as valid, and occur whenever the following happens: ? the destination segment counter in the segment control register reaches its end limit during writes to the comparand or mask registers. ? after a command write of a tco ct is executed (except for a software reset), so that a compare is executed with the new settings of the control register. forced compares are initiated by cmp instructions using one of the four validity conditions, v, r, s, and e. the forced compare against empty locations automatically masks all 128 bits of data to find all locations with the validity bits set to empty, while the other forced compares are only masked as selected in the control register. vertical cascading lancam mps can be vertically cascaded to increase system depth. through the use of flag daisy-chaining, multiple devices will respond as an integrated system. the flag daisy chain allows all commands to be issued globally, with a response only in the device containing the highest-priority matching or next free location. when connected in a daisy chain, the last devices full flag and match flag accurately report the condition for the whole string. a system in which lancam mps are vertically cascaded using daisy-chaining of the flags is shown in figure 1a on page 7. to operate the daisy chain, the device select registers are set to ffffh to enable all devices to execute command write and data write cycles. in normal operation, read cycles are enabled from the device with the highest-priority match by locking the daisy chain (see the locked daisy chain section). an individual device in the chain may be targeted for a read or write operation by temporarily setting the device select registers to the page address of the target device. setting the device select registers back to ffffh restores the operation of the entire daisy chain. match flag cascading the match flag daisy chain cascading is used for three purposes: first, to allow operations on highest-priority match addresses to be issued globally over the whole string; second, to provide a system wide match flag; third, to lock out all devices except the one with the highest-priority match for instructions such as status reads after a match. the match flag logic causes only the highest-priority device to operate on its highest- priority match location while devices with lower-priority matches ignore highest-priority match operations. the lock-out feature is enabled by the match flag cascading and the use of the /ec control signal, as shown in tables 6a and 6b on page 12. figure 5: /ec(int) timing diagram /e /ec /ec (int) /mf
mu9c1965a/l lancam a a a a a mp rev. 1a 16 device will respond (see case 6 of table 6a on page 12). if, for example, all of the cam memory locations were empty, there would be no match, and /mf would stay high. since none of the devices could then be the highest-priority match device, none will respond to reads or writes until the daisy chain is unlocked by taking /ec high and asserting /e for a cycle. if there is a match between the data in the comparand register and one or more locations in memory, then only the highest-priority match device will respond to any cycle, such as an associated data or status register read. if there is not a match, then a nop with /ec high needs to be inserted before issuing any new instructions, such as write to next free address instruction to learn the data. since next free operations are controlled by the /fiC/ff daisy chain, only the device with the first empty location will respond. if an instruction is used to unlock the daisy chain it will work only on the highest-priority match device, if one exists. if none exist, the instruction will have no effect except to unlock the daisy chain. to read the status registers of specific devices when there is no match requires the use of the tco ds command to set ds=pa of each device. single chip systems can tie /ec high and read the status register or the /ma and /mm pins to monitor match conditions, as the daisy chain lock-out feature is not needed in this configuration. this removes the need to insert a nop in the case of a no-match. when the control register is set to enhanced mode, you can continue to write data to the comparand register or issue a move to next free address instruction without first having to issue a nop with /ec high to unlock the daisy chain after a compare cycle with no match, as indicated in cases 4 and 5 of table 6b on page 12. in the enhanced mode, data write cycles as well as command write cycles are enabled in all devices even when /ec is low. exceptions are data writes, moves, or vbc instructions involving hm, which occur only in the device with the highest match; and data writes or move instructions involving nf, which occur only in the device with /fi low and /ff high. enhanced mode speeds up system performance by eliminating the need to unlock the daisy chain before command or data write cycles. the ripple delay of the flags when connected in a daisy chain requires the extension of the /e high time until the logic in all devices has settled out. in a string of n devices, the /e high time should be greater than: tehmfv + (n-2) tmivmfv if the last devices match flag is required by external logic or a state machine before the start of the next cam cycle, one additional tmivmfv should be added to the /e high time along with the setup time and delays for the external logic. locked daisy chain in a locked daisy chain, the highest-priority device is the one with /mi high and /mf low. in standard mode, only this device will respond to command and data reads and writes, until the daisy chain has been unlocked by taking /ec high. this allows reading the associated data field from only the highest-priority match location anywhere in a string of devices, or the match address from the status register of the device with the match. it also permits updating the entry stored at the highest-priority match location. in enhanced mode, devices are enabled to respond to some command and data writes, as noted in table 6b on page 12, but not command and data reads. table 6a (standard mode) and table 6b on page 12 (enhanced mode) show when a device will respond to reads or writes and when it will not, based on the state of /ec(int), the internal match condition, and other control inputs. /ec is latched by the falling edge of /e. /ec(int) is registered from the latched /ec signal off the rising edge of /e, so it controls what happens in the next cycle, as shown in figure 5. when /ec is first taken low in a string of lancam devices (and assuming the device select registers are set to ffffh), all devices will respond to that command write or data write. from then on the daisy chain will remain locked in each subsequent cycle as long as /ec is held low on the falling edge of /e in the current cycle. when the daisy chain is locked in standard mode, only the highest-priority match operational characteristics continued
mu9c1965a/l lancam a a a a a mp rev. 1a 17 full flag cascading the full flag daisy chain cascading is used for three purposes: first, to allow instructions that address next free locations to operate globally; second, to provide a system wide full flag; third, to allow the loading of the page address registers during initialization using the sff instruction. the full flag logic causes only the device containing the first empty location to respond to next free instructions such as mov nf,cr,v, which will move the contents of the comparand register to the first empty location in a string of devices and set that location valid, so it will be available for the next automatic compare. with devices connected as in figure 1a on page 7, the /ff output of the last device in a string provides a full indication for the entire string. initializing the lancam mp initialization of the lancam mp is required to configure the various registers on the device. since a control register reset establishes the operating conditions shown in table 5 on page 10, restoration of operating conditions better suited for the application may be required after a reset, whether using the control register reset, or the /reset pin. when the device powers up, the memory and registers are in an unknown state, so the /reset pin must be asserted to place the device in a known state. setting page address register values in a vertically cascaded system, the user must set the individual page address registers to unique values by using the page address initialization mechanism. each page address register must contain a unique value to prevent bus contention. this process allows individual device selection. the page address register initialization works as follows: writes to page address registers are only active for devices with /fi low and /ff high. at initialization, all devices are empty, thus the top device in the string will respond to a tco pa instruction, and load its pa register. to advance to the next device in the string, a set full flag (sff) instruction is used, which is also only active for the device with /fi low and /ff high. the sff instruction changes the first devices /ff to low, although the device really is empty, which allows the next device in the string to respond to the tco pa instruction and load its pa register. the initialization proceeds through the chain in a similar notes: 1. toggling the /reset pin generates the same effect as this reset of the control register, but good programming practice dictat es a software reset for initialization to account for all possible prior conditions. 2. this instruction may be omitted for a single lancam mp application. the last sff will cause the /ff pin in the last chip in a daisy chain to go low. in a daisy chain, ds needs to be set equal to pa to read out a particular chip prior to a match conditi on. 3. typical lancam mp control environment: enable match flag; enable full flag; 96 cam bits/32 ram bits; disable comparison masking; enable address increment; and enable enhanced mode. this example translates to 8041h. see table 9 on page 22 for control register bit assignments. 4. setting the persistent source to the memory at highest-priority match allows a compare operation to be followed by a read of the associated data when a match is found. note that the persistent destination is set to the comparand register by the reset. table 7: example initialization routine cycle type command write command write command write command write command write command write command write command write op-code tco ds tco ct tco pa sff ? ? tco ct tco ct tco sc sps m@hm dq31C16 0a28h 0a00h 0a08h 0700h 0a00h 0a00h 0a10h 0005h dq15C0 ffffh 0000h nnnnh x 0000h 8041h 3808h x comments target device select register and disable local device selection target control register and reset target page address register and set page for cascaded operation set full flag; allows access to next device (repeat previous cycle plus this one for each device in chain) target control register and reset full flags, but not page address target control register and give initial values target segment counter and set destination to use upper 3 segments (1C3) and source to only use lowest segment (0) set persistent source to memory at the highest-priority match notes 1 2 2 3 4 data bus
mu9c1965a/l lancam a a a a a mp rev. 1a 18 operational characteristics continued instruction: select persistent source (sps) binary op-code: 0000 f000 0000 0sss* f address field flag? sss selected source this instruction selects a persistent source for data reads, until another sps instruction changes it or a reset occurs. the default source after reset for data read cycles is the comparand register. setting the persistent source to m@aaah loads the address register with aaah, and the first access to that persistent source will be at aaah, after which the ar value increments or decrements as set in the control register. the sps m@[ar] instruction does the same except the current address register value is used. instruction: select persistent destination (spd) binary op-code: 0000 f001 mmdd dvvv* f address field flag? mm mask register select ddd selected destination vvv validity setting for memory location destinations this instruction selects a persistent destination for data writes, which remains until another spd instruction changes it or a reset occurs. the default destination for data write cycles is the comparand register after a reset. when the destination is the comparand register or the memory array, the data written may be masked by either mask register 1 or mask register 2, so that only destination bits corresponding to bits in the mask register set to 0 will be modified. an automatic compare will occur after writing the last segment of the comparand or mask registers, but not after writing to memory. setting the persistent destination to m@aaah loads the address register with aaah, and the first access to that persistent destination will be at aaah, after which the ar value increments or decrements as set in the control register. the spd m@[ar] instruction does the same except the current address register value is used. instruction: t emporary command override (tco) binary op-code: 0000 f010 00dd d000* f address field flag? ddd register selected as source or destination for only the next command read or write cycle the tco instruction temporarily redirects the dq bus for register access. if f=1, a register write will be performed with the data on dq15C0. if f=0, a subsequent command read cycle reads the register contents through dq15C0. during register reads, dq31C16 will contain the upper 16-bits of the status register, except in the case of a page address register read where these bits are 0s. after the access, subsequent command read or write cycles revert to reading the status register and writing to the instruction decoder. all registers except the status, nf, ps, and pd are available for write access. all registers are available for manner filling all the pa registers in turn. each device must have a unique page address value stored in its pa register, or contention will result. after all the pa registers are filled, the entire string is reset through the control register, which does not change the values stored in the individual pa registers. after the reset, the device select registers are usually set to ffffh to enable operation in case 1 of table 6a on page 12. the control registers and the segment control registers are then set to their normal operating values for the application. vertically cascaded system initialization table 7 shows an example of code that initializes a daisy- chained string of lancam mp devices. the initialization example shows how to set the page address registers of each of the devices in the chain through the use of the set full flag instruction, and how the control registers and segment counters of all the lancam mp devices are set for a typical application. each page address register must contain a unique value (not ffffh) to prevent bus contention. for typical daisy chain operation, data is loaded into the comparand registers of all the devices in a string simultaneously by setting ds=ffffh. since reading is prohibited when ds=ffffh except for the device with a match, for a diagnostic operation you need to select a specific device by setting ds=pa for the desired device to be able to read from it. refer to tables 6a and 6b on page 12 for preconditions for reading and writing. initialization for a single lancam mp is similar. the device select register in this case is usually set to equal the page address register for normal operations. also, the dedicated /ma flag output can be used instead of /mf, allowing /ec to be tied high. instruction set descriptions
mu9c1965a/l lancam a a a a a mp rev. 1a 19 instruction set descriptions continued read access. the complete status register is only available through a non-tco command read access. reading the ps register also outputs the device id on bits 15C4, as shown in table 13 on page 23. instruction: data move (mov) binary op-code: 0000 f011 mmdd dsss* or 0000 f011 mmdd dvss* f address field flag? mm mask register select ddd destination of data sss source of data v validity setting if destination is a memory location the mov instruction performs a 128-bit move of the data in the selected source to the selected destination. if the source or destination is aaah, the address register is set to aaah. for mov instructions to or from aaah or [ar], the address register will increment or decrement from that value after the move completes, as set in the control register. data transfers between the memory array and the comparand register may be masked by either mask register 1 or mask register 2, in which case, only those bits in the destination which correspond to bits in the selected mask register set to 0 will be changed. a memory location used as a destination for a mov instruction may be set to valid or left unchanged. if the source and destination are the same register, no net change occurs (a nop). instruction: validity bit control (vbc) binary op-code: 0000 f100 00dd dvvv* f address field flag? ddd destination of data vvv validity setting for memory location the vbc instruction sets the validity bits at the selected memory locations to the selected state. this feature can be used to find all valid entries by using a repetitive sequence of cmp v through a mask of all 1s followed by a vbc hm, s. if the vbc target is aaah, the address register is set to aaah. for vbc instructions to or from aaah or [ar], the address register will increment or decrement from that value after the operation completes, as set in the control register. instruction: compare (cmp) binary op-code: 0000 0101 0000 0vvv* vvv validity condition a cmp v, s, or r instruction forces a comparison of valid, skipped, or random entries against the comparand register through a mask register, if one is selected. during a cmp e instruction, the compare is only done on the validity bits and all data bits are automatically masked. instruction: special instructions binary op-code: 0000 0110 00dd drrr* ddd target resource rrr operation these instructions are a special set for the a or l lancam mp to accommodate the added features over the mu9c1485. two alternate sets of configuration registers can be selected by using the select foreground and select background registers instructions. these registers are the control, segment control, address, mask register 1, and the ps and pd registers. an rsc instruction resets the segment control register count values for both the destination and source counters to the original start limits. the shift instructions shift the designated register one bit right or left. the right and left limits for shifting are determined by the cam/ram partitioning set in the control register. the comparand register is a barrel-shifter, and for the example of a device set to 128 bits of cam executing a shift comparand right instruction, bit 0 is moved to bit 127, bit 1 is moved to bit 0, and bit 127 is moved to bit 126. for a shift comparand left instruction, bit 127 is moved to bit 0, bit 0 is moved to bit 1, and bit 126 is moved to bit 127. mr2 acts as a sliding mask, where for a shift right instruction bit 1 is moved to bit 0, while bit 0 falls off the end, and bit 127 is replicated to bit 126. for a shift mask left instruction, bit 0 is replicated to bit 1, bit 126 is moved to bit 127, and bit 127 falls off the end. with shorter width cam fields, the bit limits on the right or left move to match the width of cam field. instruction: set full flag (sff) binary op-code: 0000 0111 0000 0000* the sff instruction is a special instruction used to force the full flag low to permit setting the page address register in vertically cascaded systems. notes: instruction cycle lengths given in table 8 on page 22. * instruction op-codes are loaded on the dq31C16 lines. ? if f=1, the instruction requires an absolute address (or register contents for tcos) to be supplied on the dq15C0 lines. supplied addresses will update the address register to the aaah value supplied. during operations involving m@[ar] or m@aaah, the address register will be incremented or decremented depending on the setting in the control register.
mu9c1965a/l lancam a a a a a mp rev. 1a 20 instruction set summary mnemonic format ins dst,src[msk],val ins: instruction mnemonic dst: destination of the data src: source of the data msk: mask registser used val: validity condition set at the location written instruction: select persistent source operation mnemonic op-code comparand register sps cr 0000h mask register 1 sps mr1 0001h mask register 2 sps mr2 0002h memory array at addr. reg. sps m@[ar] 0004h memory array at address sps m@aaah 0804h mem. at highest-prio. match sps m@hm 0005h instruction: select persistent destination operation mnemonic op-code comparand register spd cr 0100h masked by mr1 spd cr[mr1] 0140h masked by mr2 spd cr[mr2] 0180h mask register 1 spd mr1 0108h mask register 2 spd mr2 0110h mem. at addr. reg. set valid spd m@[ar],v 0124h masked by mr1 spd m@[ar][mr1],v 0164h masked by mr2 spd m@[ar][mr2],v 01a4h mem. at addr. reg. set empty spd m@[ar],e 0125h masked by mr1 spd m@[ar][mr1],e 0165h masked by mr2 spd m@[ar][mr2],e 01a5h mem. at addr. reg. set skip spd m@[ar],s 0126h masked by mr1 spd m@[ar][mr1],s 0166h masked by mr2 spd m@[ar][mr2],s 01a6h mem. at addr. reg. set random spd m@[ar],r 0127h masked by mr1 spd m@[ar][mr1],r 0167h masked by mr2 spd m@[ar][mr2],r 01a7h memory at address set valid spd m@aaah,v 0924h masked by mr1 spd m@aaah[mr1],v 0964h masked by mr2 spd m@aaah[mr2],v 09a4h memory at addr. set empty spd m@aaah,e 0925h masked by mr1 spd m@aaah[mr1],e 0965h masked by mr2 spd m@aaah[mr2],e 09a5h memory at address set skip spd m@aaah,s 0926h masked by mr1 spd m@aaah[mr1],s 0966h masked by mr2 spd m@aaah[mr2],s 09a6h mem. at address set random spd m@aaah,r 0927h masked by mr1 spd m@aaah[mr1],r 0967h masked by mr2 spd m@aaah[mr2],r 09a7h mem. at highest-prio. match, valid spd m@hm,v 012ch masked by mr1 spd m@hm[mr1],v 016ch masked by mr2 spd m@hm[mr2],v 01ach instruction: select persistent destination cont. operation mnemonic op-code mem. at highest-prio. match, emp. spd m@hm,e 012dh masked by mr1 spd m@hm[mr1],e 016dh masked by mr2 spd m@hm[mr2],e 01adh mem. at highest-prio. match, skip spd m@hm,s 012eh masked by mr1 spd m@hm[mr1],s 016eh masked by mr2 spd m@hm[mr2],s 01aeh mem. at high.-prio. match, random spd m@hm,r 012fh masked by mr1 spd m@hm[mr1],r 016fh masked by mr2 spd m@hm[mr2],r 01afh mem. at next free addr., valid spd m@nf,v 0134h masked by mr1 spd m@nf[mr1],v 0174h masked by mr2 spd m@nf[mr2],v 01b4h mem. at next free addr., empty spd m@nf,e 0135h masked by mr1 spd m@nf[mr1],e 0175h masked by mr2 spd m@nf[mr2],e 01b5h mem. at next free addr., skip spd m@nf,s 0136h masked by mr1 spd m@nf[mr1],s 0176h masked by mr2 spd m@nf[mr2],s 01b6h mem. at next free addr., random spd m@nf,r 0137h masked by mr1 spd m@nf[mr1],r 0177h masked by mr2 spd m@nf[mr2],r 01b7h instruction: temporary command override operation mnemonic op-code control register tco ct 0n00h page address register tco pa 0n08h segment control register tco sc 0n10h read next free address tco nf 0218h address register tco ar 0n20h device select register tco ds 0n28h read persistent source tco ps 0230h read persistent destination tco pd 0238h *note: n = 2 for register read access n = a for register write access instruction: data move operation mnemonic op-code comparand register from: no operation nop 0300h mask register 1 mov cr,mr1 0301h mask register 2 mov cr,mr2 0302h memory at address reg. mov cr,[ar] 0304h masked by mr1 mov cr,[ar][mr1] 0344h masked by mr2 mov cr,[ar][mr2] 0384h memory at address mov cr,aaah 0b04h masked by mr1 mov cr,aaah[mr1] 0b44h masked by mr2 mov cr,aaah[mr2] 0b84h mem. at highest-prio. match mov cr,hm 0305h masked by mr1 mov cr,hm[mr1] 0345h masked by mr2 mov cr,hm[mr2] 0385h * * * *
mu9c1965a/l lancam a a a a a mp rev. 1a 21 instruction set summary continued instruction: data move continued operation mnemonic op-code mask register 1 from: comparand register mov mr1,cr 0308h no operation nop 0309h mask register 2 mov mr1,mr2 030ah memory at address reg. mov mr1,[ar] 030ch memory at address mov mr1,aaah 0b0ch mem. at highest-prio. match mov mr1,hm 030dh mask register 2 from: comparand register mov mr2,cr 0310h mask register 1 mov mr2,mr1 0311h no operation nop 0312h memory at address reg. mov mr2,[ar] 0314h memory at address mov mr2,aaah 0b14h mem. at highest-prio. match mov mr2,hm 0315h memory at address register, no change to validity bits, from: comparand register mov [ar],cr 0320h masked by mr1 mov [ar],cr[mr1] 0360h masked by mr2 mov [ar],cr[mr2] 03a0h mask register 1 mov [ar],mr1 0321h mask register 2 mov [ar],mr2 0322h memory at address register, location set valid, from: comparand register mov [ar],cr,v 0324h masked by mr1 mov [ar],cr[mr1],v 0364h masked by mr2 mov [ar],cr[mr2],v 03a4h mask register 1 mov [ar],mr1,v 0325h mask register 2 mov [ar],mr2,v 0326h memory at address, no change to validity bits, from: comparand register mov aaah,cr 0b20h masked by mr1 mov aaah,cr[mr1] 0b60h masked by mr2 mov aaah,cr[mr2] 0ba0h mask register 1 mov aaah,mr1 0b21h mask register 2 mov aaah,mr2 0b22h memory at address, location set valid, from: comparand register mov aaah,cr,v 0b24h masked by mr1 mov aaah,cr[mr1],v 0b64h masked by mr2 mov aaah,cr[mr2],v 0ba4h mask register 1 mov aaah,mr1,v 0b25h mask register 2 mov aaah,mr2,v 0b26h memory at highest-priority match, no change to validity bits, from: comparand register mov hm,cr 0328h masked by mr1 mov hm,cr[mr1] 0368h masked by mr2 mov hm,cr[mr2] 03a8h mask register 1 mov hm,mr1 0329h mask register 2 mov hm,mr2 032ah memory at highest-priority match, location set valid, from: comparand register mov hm,cr,v 032ch masked by mr1 mov hm,cr[mr1],v 036ch masked by mr2 mov hm,cr[mr2],v 03ach mask register 1 mov hm,mr1,v 032dh mask register 2 mov hm,mr2,v 032eh memory at next free address, no change to validity bits, from: comparand register mov nf,cr 0330h masked by mr1 mov nf,cr[mr1] 0370h masked by mr2 mov nf,cr[mr2] 03b0h mask register 1 mov nf,mr1 0331h mask register 2 mov nf,mr2 0332h memory at next free address, location set valid, from: comparand register mov nf,cr,v 0334h masked by mr1 mov nf,cr[mr1],v 0374h masked by mr2 mov nf,cr[mr2],v 03b4h mask register 1 mov nf ,mr1,v 0335h mask register 2 mov nf ,mr2,v 0336h instruction: validity bit control operation mnemonic op-code set validity bits at address register set valid vbc [ar],v 0424h set empty vbc [ar],e 0425h set skip vbc [ar],s 0426h set random access vbc [ar],r 0427h set validity bits at address set valid vbc aaah,v 0c24h set empty vbc aaah,e 0c25h set skip vbc aaah,s 0c26h set random access vbc aaah,r 0c27h set validity bits at highest-priority match set valid vbc hm,v 042ch set empty vbc hm,e 042dh set skip vbc hm,s 042eh set random access vbc hm,r 042fh set validity bits at all matching locations set valid vbc alm,v 043ch set empty vbc alm,e 043dh set skip vbc alm,s 043eh set random access vbc alm,r 043fh instruction: compare operation mnemonic op-code compare valid locations cmp v 0504h compare empty locations cmp e 0505h compare skipped locations cmp s 0506h comp. random access locations cmp r 0507h instruction: special instructions operation mnemonic op-code shift comparand right sft cr, r 0600h shift comparand left sft cr, l 0601h shift mask register 2 right sft m2, r 0610h shift mask register 2 left sft m2, l 0611h select foreground registers sfr 0618h select background registers sbr 0619h reset seg. cont. reg. to initial val. rsc 061ah instruction: miscellaneous instructions operation mnemonic op-code no operation nop 0300h set full flag sff 0700h
mu9c1965a/l lancam a a a a a mp rev. 1a 22 instruction set summary continued table 8: instruction cycle lengths cycle length short medium long command read status register or 16-bit register data write comparand register (not last segment) mask register (not last segment) memory array (nfa invalid) memory array (nfa valid) comparand register (last segment) mask register (last segment) data read comparand register mask register memory array note: the specific timing requirements for short, medium, and long cycles are given in the switching characteristics section under the teleh parameter. for two cycle tco reads of a registers contents, the first cycle (command write tco) is short,and the second cycle (command read) is medium. cycle type command write mov reg, reg tco reg (except ct) tco ct (non-reset, hma invalid) sps, spd, sfr sbr, rsc, nop sft (a) mov reg, mem tco ct (reset) vbc (nfa invalid) sft (l) mov mem, reg tco ct (non-reset, hma valid) cmp sff vbc (nfa valid) register bit assignments table 9: control register bit assignments note: d15 reads back as 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rst r e s e t = 0 match flag enable = 00 disable = 01 no change = 11 full flag enable = 00 disable = 01 no change = 11 reserved must be set = 00 cam/ram part. 128 cam/0 ram = 000 96 cam/32 ram = 001 64 cam/64 ram = 010 32 cam/96 ram = 011 96 ram/32 cam = 100 64 ram/64 cam = 101 32 ram/96 cam = 110 no change = 111 comp. mask none = 00 mr1 = 01 mr2 = 10 no change = 11 ar inc/dec increment = 00 decrement = 01 disable = 10 no change = 11 mode standard mode = 00 enhanced mode = 01 reserved = 10 no change = 11
mu9c1965a/l lancam a a a a a mp rev. 1a 23 register bit assignments continued /ma /mm /fl skip empty page address bits, pa15Cpa6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109876543210 page address, pa5C0 next free address, nf9C0 table 11: next free address register bit assignments note: the next free address register is read only, and is accessed by performing a command read cycle immediately following a tco nf instruction. 0 ssl 12 table 10: segment control register bit assignments 15 set dest. seg. limits = 0 no chng. = 1 14 13 11 10 set source seg. limits = 0 no chng. = 1 9 8 7 65 load dest. seg. count = 0 no chng. = 1 4 3 2 load src. seg. count = 0 no chng. = 1 10 note: d15, d10, d5, and d2 read back as 0s. destination count start limit 00C11 destination count end limit 00C11 source count start limit 00C11 source count end limit 00C11 destination seg. count value 00C11 source seg. count value 00C11 sdc dcsl dcel scsl scel ldc dscv lsc sscv table 13: persistent source register bit assignments /ma /mm /fl skip empty page address bits, pa15Cpa6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 device id = 196h ps note: the persistent source register is read only, and is accessed by performing a command read cycle immediately following a tco ps instruction. 0 9 table 12: status register bit assignments note: the status register is read only, and is accessed by performing a command read cycle. 151413121110 876543210 pa5Cpa0 match address, am9Cam0 /ma /mm /fl skip empty page address bits, pa15Cpa6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0
mu9c1965a/l lancam a a a a a mp rev. 1a 24 operating conditions (voltages referenced to gnd at the device pin) symbol v cc v ih v il t a parameter operating supply voltage input voltage logic 1 input voltage logic 0 ambient operating temperature min 4.75 3.0 2.0 -0.5 0 typical 5.0 3.3 max 5.25 3.6 v cc + 0.5 0.8 70 notes 1, 2 still air 1965a 1965l units volts volts volts volts c absolute maximum ratings supply voltage 1965a -0.5 to 7.0 volts 1965l -0.5 to 4.6 volts voltage on all other pins -0.5 to vcc +0.5 volts (-2 volts for 10 ns, measured at the 50% point) temperature under bias -40c to +85c storage temperature -55c to 125c dc output current 20 ma (per output, one at a time, one second duration. stresses exceeding those listed under absolute maximum ratings may include failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. all voltages referenced to gnd. operational characteristics capacitance symbol c in c out parameter input capacitance output capacitance max 6 7 notes f = 1 mhz, v in = 0 v f = 1 mhz, v out = 0 v units pf pf dc electrical characteristics min 2.4 -2 6 6 -10 typical 150 100 9 10 max 275 150 7 2 0.4 +2 12 13 10 symbol i cc i cc(sb) v oh v ol i iz i oz parameter average power supply current stand-by power supply current output voltage logic 1 output voltage logic 0 input leakage current output leakage current units ma ma ma ma volts volts m a kohms kohms m a notes /e = high v cc = max i oh = -2.0ma i ol = 4.0ma v ss v in v cc v in = 0 v v in = v cc ;10 v ss v out v cc; dq n = high impedance 1965a 1965l 1965a 1965l others /reset test1,test2 telel=telel(min);9
mu9c1965a/l lancam a a a a a mp rev. 1a 25 operational characteristics continued input signal transitions 0.0 volts to 3.0 volts input signal rise time < 3 ns. input signal fall time < 3 ns. input timing reference level 1.5 volts output timing reference level 1.5 volts ac test conditions switching test figures component values figure 6: ac test load figure 7: input signal waveform switching test figures to device under test r2 vc c r1 c1 inpu t waveform 0v v il ( min ) 10ns 50% a m plitude point parameter vcc r1 r2 c1 (includes jig) test load a test load b 1965a 1965l 5.0 961 510 30 5 3.3 635 702 30 5 volts ohm ohm pf pf units
mu9c1965a/l lancam a a a a a mp rev. 1a 26 parameter (all times in nanoseconds) chip enable compare cycle time chip enable low short cycle: pulse width medium cycle: long cycle: chip enable high pulse width control input to chip enable low set-up time control input from chip enable low hold time chip enable low to outputs active chip enable low to outputs valid chip enable high to outputs high-z data to chip enable low set-up time data from chip enable low hold time full in valid to chip enable low set-up time full in valid to full flag valid chip enable low to full flag valid match in valid to chip enable low set-up time chip enable high to /mf, /ma, /mm invalid match in valid to /mf, /mm, valid chip enable high to /mf valid chip enable high to /ma and /mm valid reset low pulse width min 50 15 30 45 5 0 10 3 3 0 10 0 0 0 50 max 30 40 10 5 35 4 16 18 no 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 symbol t elel t eleh t ehel t cvel t elcx t elqx t elqv t ehqz t dvel t eldx t fivel t fivffv t elffv t mivel t ehmfx t mivmfv t ehmfv t ehmxv t rlrh notes 4 4 4 5 5 6 4,6 4,6 7 8 max 70 85 20 8 90 8 30 30 min 120 35 75 100 20 0 15 3 3 0 15 0 0 0 100 max 50 75 15 7 75 7 25 25 min 90 25 50 75 15 0 10 3 3 0 10 0 0 0 100 max 30 52 10 5 50 5 16 18 min 70 15 35 55 15 0 10 3 3 0 10 0 0 0 100 -70 -90 -12 notes: 1. -1.0v for a duration of 10 ns measured at the 50% amplitude points for input-only lines (figure 7). 2. common i/o lines are clamped, so that signal transients cannot fall below -0.5v. 3. at 0C70 c and vcc(min) to vcc(max). 4. see table 8 on page 22. 5. control signals are /w, /cm, and /ec. 6. with load specified in figure 6, test load a. 7. with load specified in figure 6, test load b. 8. /e must be high during this period to ensure accurate default values in the configuration registers. 9. with output and i/o pins unloaded. 10. test1 and/or test2 many not be implemented on all versions of these products. cycle time a devices l devices operational characteristics continued switching characteristics (see note 3) -50 available consult factory for availability
mu9c1965a/l lancam a a a a a mp rev. 1a 27 1 /e /w /c m 4 4 valid /m a , /m m 14 2 3 5 5 /e c 4 5 /m f /m i 18 17 16 15 timing diagrams read cycle write cycle compare cycle /e /w /cm /ec dq31-0 2 3 4 5 4 5 8 6 4 5 7 /e /w /cm /ec dq31-0 23 4 5 4 5 4 10 13 9 12 11 /fi /ff 5
mu9c1965a/l lancam a a a a a mp rev. 1a 28 ordering information package outline dimensions are in mm. 80-pin tqfp dim. a1 dim. a2 dim. b dim. c dim. d dim. e dim. e dim. hd dim.he dim. l dim. l1 0.22 0.38 13.90 14.10 13.90 14.10 0.65 nom 15.90 16.10 15.90 16.10 0.45 0.75 1.00 nom 0.05 0.15 0.08 0.20 1.35 1.45 a2 a1 hd d e he l b e c l1 part number mu9c1965a - 50tcc mu9c1965a - 70tcc mu9c1965a - 90tcc mu9c1965a - 12tcc mu9c1965l - 50tcc mu9c1965l - 70tcc mu9c1965l - 90tcc mu9c1965l - 12tcc cycle time 50ns 70ns 90ns 120ns 50ns 70ns 90ns 120ns package 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp 80-pin tqfp temperature 0C70 c 0C70 c 0C70 c 0C70 c 0C70 c 0C70 c 0C70 c 0C70 c voltage 5.0 .25 5.0 .25 5.0 .25 5.0 .25 3.3 0.3 3.3 0.3 3.3 0.3 3.3 0.3 consult factory for availability 0.25 l gage plane european headquarters music semiconductors torenstraat 28 6471 jx eygelshoven netherlands tel: +31 45 5462177 fax: +31 45 5463663 music semiconductors reserves the right to make changes to its products and specifications at any time in order to improve on performance, manufacturability, or reliability. information furnished by music is believed to be accurate, but no responsibility is assumed by music semiconductors for the use of said information, nor for any infringement of patents or of other third party rights which may result from said use. no license is granted by implication or otherwise under any patent or patent rights of any music company. ?copyright 1998, music semiconductors music semiconductors agent or distributor: usa headquarters music semiconductors 254 b mountain avenue hackettstown, new jersey 07840 usa tel: 908/979-1010 fax: 908/979-1035 usa only: 800/933-1550 tech. support 888/226-6874 product info. asian headquarters music semiconductors special export processing zone 1 carmelray industrial park canlubang, calamba, laguna philippines tel: +63 49 549 1480 fax: +63 49 549 1023 sales tel/fax: +632 723 62 15 http://www.music-ic.com email: info@music-ic.com

▲Up To Search▲

Price & Availability of MU9C1965L-50TCC

	To Download MU9C1965L-50TCC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .